1. Field of the Invention
The present invention relates to an apparatus for driving capacitive light emitting elements.
2. Description of the Related Art
Nowadays, display panels comprising capacitive light emitting elements such as a plasma display panel (hereinafter referred to as the “PDP”), an electroluminescence display panel (hereinafter referred to as the “ELP”) and the like have been brought into practical use to provide wall-mounted television sets.
FIG. 1 generally shows such a plasma display panel which has a PDP as a display panel (see, for example, FIG. 3 of Japanese Patent Kokai No. 2002-156941).
In FIG. 1, a PDP 10 as a plasma display panel comprises row electrodes Y1-Yn and X1-Xn which form pairs of row electrodes X, Y, each of which corresponds to each of a first to an n-th row of one screen. The PDP 10 is further formed with column electrodes Z1-Zm corresponding to respective columns (first to m-th columns) of one screen, which are orthogonal to the row electrode pairs and across a dielectric layer and a discharge space, not shown. A discharge cell serving as a pixel is formed at the intersection of a pair of row electrodes (X, Y) with a column electrode Z.
A row electrode driving circuit 30 generates a sustain pulse for repeatedly discharging a discharge cell which has a wall charge remaining therein, and applies the sustain pulse to the row electrodes X1-Xn of the PDP 10. A row electrode driving circuit 40 generates a reset pulse for initializing the states of all the discharge cells, a scanning pulse for sequentially selecting a display line into which pixel data is written, and a sustain pulse for repeatedly discharging a discharge cell which has a wall charge remaining therein, and applies these pulses to the row electrodes Y1-Yn.
A driving control circuit 50 converts an input video signal, for example, to 8-bit pixel data for each pixel which is divided for each bit digit to generate pixel data bits. Then, the driving control circuit 50 supplies a column electrode driving circuit 20 with pixel data bits DB1-DBm corresponding to the first to m-th columns belonging to each display line. Further, in this period, the driving control circuit 50 generates switching signals SW1-SW3, as shown in FIG. 2, which are supplied to the column electrode driving circuit 20.
FIG. 3 is a diagram showing the internal configuration of the column electrode driving circuit 20.
As shown in FIG. 3, the column electrode driving circuit 20 comprises a power supply circuit 21 for generating a resonance pulse power supply voltage having a predetermined amplitude and applying a power supply line 2 with the resonance pulse power supply voltage; and a pixel data pulse generating circuit 22 for generating a pixel data pulse based on the resonance pulse power supply voltage.
A capacitor C1 in the power supply circuit 21 has one electrode connected to a ground potential Vs as a ground potential for the PDP 10. A switching element S1 is controlled to turn on/off in response to the switching signal SW1. In this event, as the switching element S1 turns on, a voltage generated on the other electrode of the capacitor C1 is applied to the power supply line 2 through a coil L1 and a diode D1. A switching element S2 is controlled to turn on/off in response to the switching signal SW2. In this event, as the switching element S2 turns on, a voltage on the power supply line 2 is applied to the other electrode of the capacitor C1 through a coil L2 and a diode D2 to charge the capacitor C1. A switching element S3 is controlled to turn on/off in response to the switching signal SW3. In this event, as the switching element S3 turns on, a power supply voltage Va generated by a DC power supply B1 is applied to the power supply line 2. The DC power supply B1 has a negative electrode terminal grounded at the ground potential Vs.
The power supply circuit 21, which operates as described above, results in the generation of the resonance pulse power supply voltage, on the power supply line 2, having a maximum voltage equal to the power supply voltage Va, and a resonance amplitude V1, as shown in FIG. 2.
A pixel data pulse generator circuit 22 has switching elements SWZ1-SWZm and SWZ10-SWZm0 which are controlled independently of one another to turn on/off in response to associated pixel data bits DB1-DBm of one display line (m bits) supplied from the driving control circuit 50. Each of the switching elements SWZ1-SWZm turns on when the pixel data bit DB supplied thereto is at logical level “1” to supply the resonance pulse power supply voltage on the power supply line 2 to the column electrodes Z1-Zm.
Here, the switching elements S1-S3, which are switched to generate the resonance pulse power supply voltage, are each actually comprised of FET (Field Effect Transistor). In this event, the switching element S2 performs a switching operation with a reference potential which is the potential on the one electrode of the capacitor C1. For this reason, a capacitor having a large capacitance has been employed for the capacitor C1 in order to reduce fluctuations in the reference potential to stabilize the switching operation of the switching element S2.
However, a capacitor having a large capacitance is large in shape, implying a problem that a resulting driving apparatus is increased in size.